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publication number 21635 revision c amendment +3 issue date november 1, 2004 july 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. am29sl160c data sheet
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this data sheet states amd?s current specifications regarding the products described herein. this data sheet may be revised by subsequent versions or modifications due to changes in technical specifications. publication# 21635 rev: c amendment/ +3 issue date: november 1, 2004 refer to amd?s website (www.amd.com) for the latest information. am29sl160c 16 megabit (2 m x 8-bit/1 m x 16-bit) cmos 1.8 volt-only super low voltage flash memory distinctive characteristics architectural advantages secured silicon (secsi) sector: 256-byte sector ? factory locked and identifiable: 16 bytes available for secure, random factory electronic serial number; verifiable as factory locked through autoselect function. expressflash option allows entire sector to be available for factory-secured data ? customer lockable: customer may program own custom data. once locked, data cannot be changed zero power operation ? sophisticated power management circuits reduce power consumed during inactive periods to nearly zero package options ? 48-ball fbga ? 48-pin tsop top or bottom boot block manufactured on 0.32 m process technology compatible with jedec standards ? pinout and software compatible with single-power- supply flash standard performance characteristics high performance ? access time as fast 90 ns ? program time: 8 s/word typical using accelerate ultra low power consumption (typical values) ? 1 ma active read current at 1 mhz ? 5 ma active read current at 5 mhz ? 1 a in standby or automatic sleep mode minimum 1 million erase cycles guaranteed per sector 20 year data retention at 125 c ? reliable operation for the life of the system software features supports common flash memory interface (cfi) erase suspend/erase resume ? suspends erase operations to allow programming in same bank data# polling and toggle bits ? provides a software method of detecting the status of program or erase cycles unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features any combination of sectors can be erased ready/busy# output (ry/by#) ? hardware method for detecting program or erase cycle completion hardware reset pin (reset#) ? hardware method of resetting the internal state machine to reading array data wp#/acc input pin ? write protect (wp#) function allows protection of two outermost boot sectors, regardless of sector protect status ? acceleration (acc) function accelerates program timing sector protection ? hardware method of locking a sector, either in- system or using programming equipment, to prevent any program or erase operation within that sector ? temporary sector unprotect allows changing data in protected sectors in-system
4 am29sl160c november 1, 2004 general description the am29sl160c is a 16 mbit, 1.8 v volt-only flash memory organized as 2,097,152 bytes or 1,048,576 words. the data appears on dq0?dq15. the device is offered in 48-pin tsop and 48-ball fbga packages. the word-wide data (x16) appears on dq15?dq0; the byte-wide (x8) data appears on dq7?dq0. this device is designed to be programmed and erased in-system with a single 1.8 volt v cc supply. no v pp is required for program or erase operations. the device can also be programmed in standard eprom programmers. the standard device offers access times of 90, 100, 120, or 150 ns, allowing microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device requires only a single 1.8 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard . com- mands are written to the command register using standard microprocessor write timings. register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm?an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. the unlock bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase command sequence. this initiates the embedded erase algorithm?an internal algorithm that automati- cally preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by observing the ry/by# pin, or by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle completes, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector pro- tection feature disables both program and erase operations in any combination of the sectors of memory. this is achieved in-system or via program- ming equipment. the erase suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the flash memory. the device offers two power-saving features. when addresses are stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both modes. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection.
november 1, 2004 am29sl160c 5 table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 7 special handling instructions for fbga packages .................. 8 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ordering information . . . . . . . . . . . . . . . . . . . . . . 10 table 1. am29sl160c device bus operations .............................11 word/byte configuration ........................................................ 11 requirements for reading array data ................................... 11 writing commands/command sequences ............................ 12 accelerated program operation ............................................. 12 program and erase operation status .................................... 12 standby mode ........................................................................ 12 automatic sleep mode ........................................................... 12 reset#: hardware reset pin ............................................... 12 output disable mode .............................................................. 13 table 2. am29sl160ct top boot sector architecture ..................14 table 3. am29sl160cb bottom boot sector architecture .............15 autoselect mode ..................................................................... 16 table 4. am29sl160c autoselect codes (high voltage method) ..16 sector/sector block protection and unprotection .................. 17 table 5. top boot sector/sector block addresses for protection/unprotection .............................................................17 table 6. bottom boot sector/sector block addresses for protection/unprotection ...........................................17 write protect (wp#) ................................................................ 18 temporary sector unprotect .................................................. 18 figure 1. in-system sector protect/unprotect algorithms .............. 19 figure 2. temporary sector unprotect operation........................... 20 secured silicon (secsi) sector flash memory region .......... 20 table 7. secsi sector addresses ...................................................20 hardware data protection ...................................................... 20 low v cc write inhibit .............................................................. 20 write pulse ?glitch? protection ............................................... 20 logical inhibit .......................................................................... 20 power-up write inhibit ............................................................ 20 common flash memory interface (cfi) . . . . . . . 21 table 8. cfi query identification string ..........................................21 table 9. system interface string .....................................................22 table 10. device geometry definition ............................................22 table 11. primary vendor-specific extended query ......................23 command definitions . . . . . . . . . . . . . . . . . . . . . 23 reading array data ................................................................ 23 reset command ..................................................................... 23 autoselect command sequence ............................................ 24 enter secsi sector/exit secsi sector command sequence .. 24 word/byte program command sequence ............................. 24 unlock bypass command sequence ..................................... 24 figure 3. program operation .......................................................... 25 chip erase command sequence ........................................... 26 sector erase command sequence ........................................ 26 erase suspend/erase resume commands ........................... 26 figure 4. erase operation.............................................................. 27 command definitions ............................................................. 28 table 12. am29sl160c command definitions ............................. 28 write operation status . . . . . . . . . . . . . . . . . . . . 29 dq7: data# polling ................................................................. 29 figure 5. data# polling algorithm .................................................. 29 ry/by#: ready/busy# ............................................................ 30 dq6: toggle bit i .................................................................... 30 dq2: toggle bit ii ................................................................... 30 reading toggle bits dq6/dq2 ............................................... 30 dq5: exceeded timing limits ................................................ 31 dq3: sector erase timer ....................................................... 31 figure 6. toggle bit algorithm........................................................ 31 table 13. write operation status ................................................... 32 absolute maximum ratings . . . . . . . . . . . . . . . . 33 figure 7. maximum negative overshoot waveform ...................... 33 figure 8. maximum positive overshoot waveform........................ 33 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . 33 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 9. i cc1 current vs. time (showing active and automatic sleep currents) .............................................................................. 35 figure 10. typical i cc1 vs. frequency ............................................ 35 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 11. test setup..................................................................... 36 table 14. test specifications ......................................................... 36 figure 12. input waveforms and measurement levels ................. 36 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37 read operations .................................................................... 37 figure 13. read operations timings ............................................. 37 hardware reset (reset#) .................................................... 38 figure 14. reset# timings .......................................................... 38 word/byte configuration (byte#) ........................................ 39 figure 15. byte# timings for read operations............................ 39 figure 16. byte# timings for write operations............................ 39 erase/program operations ..................................................... 40 figure 17. program operation timings.......................................... 41 figure 18. chip/sector erase operation timings .......................... 42 figure 19. data# polling timings (during embedded algorithms). 43 figure 20. toggle bit timings (during embedded algorithms)...... 43 figure 21. dq2 vs. dq6................................................................. 44 figure 22. temporary sector unprotect timing diagram .............. 44 figure 23. accelerated program timing diagram.......................... 45 figure 24. sector protect/unprotect timing diagram .................... 45 figure 25. alternate ce# controlled write operation timings ...... 47 erase and programming performance . . . . . . . 48 latchup characteristics . . . . . . . . . . . . . . . . . . . . 48 tsop pin capacitance . . . . . . . . . . . . . . . . . . . . . 48 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 physical dimensions* . . . . . . . . . . . . . . . . . . . . . 49 ts 048?48-pin standard tsop ............................................ 49 fbc048?48-ball fine-pitch ball grid array (fbga) 8 x 9 mm package .................................................................. 50 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 51
6 am29sl160c november 1, 2004 product selector guide note: see ?ac characteristics? for full specifications. block diagram family part number am29sl160c speed options -90 -100 -120 -150 max access time, ns (t acc ) 90 100 120 150 max ce# access time, ns (t ce ) 90 100 120 150 max oe# access time, ns (t oe )35355065 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# byte# wp#/acc ce# oe# stb stb dq0 ? dq15 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a0?a19
november 1, 2004 am29sl160c 7 connection diagrams a1 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 nc we# reset# nc wp#/acc ry/by# a17 a7 a6 a5 a4 a3 a2 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 standard tsop
8 am29sl160c november 1, 2004 connection diagrams (continued) special handling instructions for fbga packages special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 nc reset# we# dq11 dq3 dq10 dq2 nc a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 48-ball fbga (top view, balls facing down)
november 1, 2004 am29sl160c 9 pin configuration a0?a19 = 20 addresses dq0?dq14 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# = chip enable oe# = output enable we# = write enable wp#/acc = hardware write protect/acceleration pin reset# = hardware reset pin, active low byte# = selects 8-bi t or 16-bit mode ry/by# = ready/busy# output v cc = 1.8?2.2 v single power supply v ss = device ground nc = pin not connected internally logic symbol 20 16 or 8 dq0?dq15 (a-1) a0?a19 ce# oe# we# reset# byte# ry/by# wp#/acc
10 am29sl160c november 1, 2004 ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combi- nation) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. am29sl160c t -90 e c n standard processing n = secsi sector factory-locked with random esn (contact an amd representative for more information) temperature range c = commercial (0c to +70c) i = industrial (?40 c to +85 c) e = extended (?55 c to +125 c) d= commercial (0 o c to +70 o c) with pb-free package f = industrial (-40 o c to +85 o c) with pb-free package f = extended (-55 o c to +125 o c) with pb-free package package type e = 48-pin thin small outline package (tsop) standard pinout (ts 048) wc=48-ball fine-pitch ball grid array (fbga) 0.80 mm pitch, 8 x 9 mm package (fbc048) speed option see product selector guide and valid combinations boot code sector architecture t = top sector b = bottom sector device number/description am29sl160c 16 megabit (2 m x 8-bit/1 m x 16-bit) cmos flash memory 1.8 volt-only read, program, and erase valid combinations for tsop packages am29sl160ct-90, am29sl160cb-90 ec, ei ed, ef am29sl160ct-100, am29sl160cb-100 am29sl160ct-120, AM29SL160CB-120 am29sl160ct-150, am29sl160cb-150 valid combinations for fbga packages order number package marking am29sl160ct-90, am29sl160cb-90 wcc, wci wcd, wcf a160ct90v, a160cb90v c, i, d, f am29sl160ct-100, am29sl160cb-100 a160ct10v, a160cb10v am29sl160ct-120, AM29SL160CB-120 a160ct12v, a160cb12v am29sl160ct-150, am29sl160cb-150 a160ct15v, a160cb15v
november 1, 2004 am29sl160c 11 device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is composed of latches that store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. ta b l e 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. am29sl160c device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 10 1.0 v, v hh = 10 0.5 v, x = don?t care, a in = address in, d in = data in, d out = data out notes: 1. addresses are a19:a0 in word mode (byte# = v ih ), a19:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see ?sector/sector block protection and unprotection? on page 17 . 3. if wp#/acc = v il , the two outermost boot sectors are protected. if wp#/acc = v ih , the two outermost boot sectors are protected or unprotected as previously set by the system. if wp#/acc = v hh , all sectors, including the two outermost boot sectors, are unprotected. word/byte configuration the byte# pin controls whether the device data i/o pins dq15?dq0 operate in the byte or word configura- tion. if the byte# pin is set at logic ?1?, the device is in word configuration, dq15?dq0 are active and con- trolled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/o pins dq8?dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the byte# pin determines whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array operation ce# oe# we# reset# wp#/acc addresses (note 1) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h x a in d out d out dq8?dq14 = high-z, dq15 = a-1 write (program/erase) l h l h (note 3) a in d in d in standby v cc 0.2 v xx v cc 0.2 v x x high-z high-z high-z output disable l h h h x x high-z high-z high-z reset x x x l x x high-z high-z high-z sector protect (note 2) lhl v id x sector address, a6 = l, a1 = h, a0 = l d in xx sector unprotect (note 2) lhl v id (note 3) sector address, a6 = h, a1 = h, a0 = l d in xx temporary sector unprotect xxx v id (note 3) a in d in d in high-z
12 am29sl160c november 1, 2004 data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? on page 23 for more infor- mation. refer to the ac table for timing specifications and to figure 13, on page 37 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whether the device accepts program data in bytes or words. refer to ?word/byte configuration? on page 11 for more information. the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a word or byte, instead of four. the ?word/byte program command sequence? on page 24 contains details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2, on page 14 and table 3, on page 15 indicate the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the ?command definitions? on page 23 contains details on erasing a sector or the entire chip, or sus- pending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to ?autoselect mode? on page 16 and ?autoselect command sequence? on page 24 for more information. i cc2 in the dc characteristics table represents the active current specification for the write mode. the ?ac characteristics? on page 37 contains timing specifica- tion tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operation through the acc function, which is one of two functions provided by the wp#/acc pin. this function is prima- rily intended to allow faster in-system programming of the device during the system production process. if the system asserts v hh on the pin, the device auto- matically enters the aforementioned unlock bypass mode and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to normal operation. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7?dq0. standard read cycle timings and i cc read specifications apply. refer to ?write operation status? on page 29 for more information, and to ?ac characteristics? on page 37 for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.2 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.2 v, the device is in the standby mode, but the standby current is greater. the device requires stan- dard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. the device also enters the standby mode when the reset# pin is driven low. refer to ?reset#: hard- ware reset pin? on page 12 . if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 50 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the auto- matic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of reset- ting the device to reading array data. when the
november 1, 2004 am29sl160c 13 reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current is greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase oper- ation, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algo- rithms). the system can read data t rh after the reset# pin returns to v ih . refer to ?ac characteristics? on page 37 for reset# parameters and to ?reset# timings? on page 38 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high imped- ance state.
14 am29sl160c november 1, 2004 table 2. am29sl160ct top bo ot sector architecture note: address range is a19:a-1 in byte mode and a19:a0 in word mode. see ?word/byte configuration? section for more information. sector sector address sector size (kbytes/kwords) address range (in hexadecimal a19 a18 a17 a16 a15 a14 a13 a12 byte mode (x8) word mode (x16) sa0 00000xxx 64/32 000000h?00ffffh00000h?07fffh sa1 00001xxx 64/32 010000h?01ffffh08000h?0ffffh sa2 00010xxx 64/32 020000h?02ffffh10000h?17fffh sa3 00011xxx 64/32 030000h?03ffffh18000h?1ffffh sa4 00100xxx 64/32 040000h?04ffffh20000h?27fffh sa5 00101xxx 64/32 050000h?05ffffh28000h?2ffffh sa6 00110xxx 64/32 060000h?06ffffh30000h?37fffh sa7 00111xxx 64/32 070000h?07ffffh38000h?3ffffh sa8 01000xxx 64/32 080000h?08ffffh40000h?47fffh sa9 01001xxx 64/32 090000h?09ffffh48000h?4ffffh sa1001010xxx 64/32 0a0000h?0affffh50000h?57fffh sa1101011xxx 64/32 0b0000h?0bffffh58000h?5ffffh sa1201100xxx 64/32 0c0000h?0cffffh60000h?67fffh sa1301101xxx 64/32 0d0000h?0dffffh68000h?6ffffh sa1401110xxx 64/32 0e0000h?0effffh70000h?77fffh sa1501111xxx 64/32 0f0000h?0fffffh78000h?7ffffh sa1610000xxx 64/32 100000h?10ffffh80000h?87fffh sa1710001xxx 64/32 110000h?11ffffh88000h?8ffffh sa1810010xxx 64/32 120000h?12ffffh90000h?97fffh sa1910011xxx 64/32 130000h?13ffffh98000h?9ffffh sa2010100xxx 64/32 140000h?14ffffha0000h?a7fffh sa2110101xxx 64/32 150000h?15ffffha8000h?affffh sa2210110xxx 64/32 160000h?16ffffhb0000h?b7fffh sa2310111xxx 64/32 170000h?17ffffhb8000h?bffffh sa2411000xxx 64/32 180000h?18ffffhc0000h?c7fffh sa2511001xxx 64/32 190000h?19ffffhc8000h?cffffh sa2611010xxx 64/32 1a0000h?1affffhd0000h?d7fffh sa2711011xxx 64/32 1b0000h?1bffffhd8000h?dffffh sa2811100xxx 64/32 1c0000h?1cffffhe0000h?e7fffh sa2911101xxx 64/32 1d0000h?1dffffhe8000h?effffh sa3011110xxx 64/32 1e0000h?1effffhf0000h?f7fffh sa3111111000 8/4 1f0000h?1f1fffhf8000h?f8fffh sa3211111001 8/4 1f2000h?1f3fffhf9000h?f9fffh sa3311111010 8/4 1f4000h?1f5fffhfa000h?fafffh sa3411111011 8/4 1f6000h?1f7fffhfb000h?fbfffh sa3511111100 8/4 1f8000h?1f9fffhfc0004?fcfffh sa3611111101 8/4 1fa000h?1fbfffhfd000h?fdfffh sa3711111110 8/4 1fc000h?1dffffhfe000h?fefffh sa3811111111 8/4 1fe000h?1fffffhff000h?fffffh
november 1, 2004 am29sl160c 15 table 3. am29sl160cb bottom boot sector architecture note: address range is a19:a-1 in byte mode and a19:a0 in word mode. see ?word/byte configuration? section for more information. sector sector address sector size (kbytes/kwords) address range (in hexadecimal) a19 a18 a17 a16 a15 a14 a13 a12 byte mode (x8) word mode (x16) sa0 00000000 8/4 000000h?001fffh00000h?00fffh sa1 00000001 8/4 002000h?003fffh01000h?01fffh sa2 00000010 8/4 004000h?005fffh02000h?02fffh sa3 00000011 8/4 006000h?07ffffh03000h?03fffh sa4 00000100 8/4 008000h?009fffh04000h?04fffh sa5 00000101 8/4 00a000h?00bfffh05000h?05fffh sa6 00000110 8/4 00c000h?00dfffh06000h?06fffh sa7 00000111 8/4 00e000h?00ffffh07000h?07fffh sa8 00001xxx 64/32 010000h?01ffffh08000h?0ffffh sa9 00010xxx 64/32 020000h?02ffffh10000h?17fffh sa1000011xxx 64/32 030000h?03ffffh18000h?1ffffh sa1100100xxx 64/32 040000h?04ffffh20000h?27fffh sa1200101xxx 64/32 050000h?05ffffh28000h?2ffffh sa1300110xxx 64/32 060000h?06ffffh30000h?37fffh sa1400111xxx 64/32 070000h?07ffffh38000h?3ffffh sa1501000xxx 64/32 080000h?08ffffh40000h?47fffh sa1601001xxx 64/32 090000h?09ffffh48000h?4ffffh sa1701010xxx 64/32 0a0000h?0affffh50000h?57fffh sa1801011xxx 64/32 0b0000h?0bffffh58000h?5ffffh sa1901100xxx 64/32 0c0000h?0cffffh60000h?67fffh sa2001101xxx 64/32 0d0000h?0dffffh68000h?6ffffh sa2101110xxx 64/32 0e0000h?0effffh70000h?77fffh sa2201111xxx 64/32 0f0000h?0fffffh78000h?7ffffh sa2310000xxx 64/32 100000h?10ffffh80000h?87fffh sa2410001xxx 64/32 110000h?11ffffh88000h?8ffffh sa2510010xxx 64/32 120000h?12ffffh90000h?97fffh sa2610011xxx 64/32 130000h?13ffffh98000h?9ffffh sa2710100xxx 64/32 140000h?14ffffha0000h?a7fffh sa2810101xxx 64/32 150000h?15ffffha8000h?affffh sa2910110xxx 64/32 160000h?16ffffhb0000h?b7fffh sa3010111xxx 64/32 170000h?17ffffhb8000h?bffffh sa3111000xxx 64/32 180000h?18ffffhc0000h?c7fffh sa3211001xxx 64/32 190000h?19ffffhc8000h?cffffh sa3311010xxx 64/32 1a0000h?1affffhd0000h?d7fffh sa3411011xxx 64/32 1b0000h?1bffffhd8000h?dffffh sa3511100xxx 64/32 1c0000h?1cffffhe0000h?e7fffh sa3611101xxx 64/32 1d0000h?1dffffhe8000h?effffh sa3711110xxx 64/32 1e0000h?1effffhf0000h?f7fffh sa3811111xxx 64/32 1f0000h?1fffffhf8000h?fffffh
16 am29sl160c november 1, 2004 autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins a6, a1, and a0 must be as shown in table 4 . in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see tables 2 and 3). table 4 shows the remaining address bits that are don?t care. when all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 12, on page 28 . this method does not require v id . see ?command def- initions? on page 23 for details on using the autoselect mode. table 4. am29sl160c autoselect codes (high voltage method) l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. note: outputs for data bits dq8?dq15 are for byte#=v ih . dq8?dq15 are don?t care when byte#=v il . description mode ce# oe# we# a19 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id : amd l l h x x v id xlxll x 01h device id: am29sl160ct (top boot block) word l l h xxv id xlxlh 22h e4 byte l l h x e4 device id: am29sl160cb (bottom boot block) word l l h xxv id xlxlh 22h e7 byte l l h x e7 sector protection verification l l h sa x v id xlxhl x 01h (protected) x 00h (unprotected) secsi sector indicator bit (dq7) llhsaxv id xlxhh x 81h (factory locked)
november 1, 2004 am29sl160c 17 sector/sector block protection and unprotection (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see ta b l e 5 and table 6 ). table 5. top boot sector/sector block addresses for protection/unprotection table 6. bottom boot sector/sector block addresses for protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hard- ware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection/unprotection is implemented via two methods. sector / sector block a19?a12 sector / sector block size sa0 00000xxx 64 kbytes sa1-sa3 00001xxx, 00010xxx, 00011xxx 192 (3x64) kbytes sa4-sa7 001xxxxx 256 (4x64) kbytes sa8-sa11 010xxxxx 256 (4x64) kbytes sa12-sa15 011xxxxx 256 (4x64) kbytes sa16-sa19 100xxxxx 256 (4x64) kbytes sa20-sa23 101xxxxx 256 (4x64) kbytes sa24-sa27 110xxxxx 256 (4x64) kbytes sa28-sa30 11100xxx, 11101xxx, 11110xxx 192 (3x64) kbytes sa31 11111000 8 kbytes sa32 11111001 8 kbytes sa33 11111010 8 kbytes sa34 11111011 8 kbytes sa35 11111100 8 kbytes sa36 11111101 8 kbytes sa37 11111110 8 kbytes sa38 11111111 8 kbytes sector / sector block a19?a12 sector / sector block size sa38 11111xxx 64 kbytes sa37-sa35 11110xxx, 11101xxx, 11100xxx 192 (3x64) kbytes sa34-sa31 110xxxxx 256 (4x64) kbytes sa30-sa27 101xxxxx 256 (4x64) kbytes sa26-sa23 100xxxxx 256 (4x64) kbytes sa22-sa19 011xxxxx 256 (4x64) kbytes sa18-sa15 010xxxxx 256 (4x64) kbytes sa14-sa11 001xxxxx 256 (4x64) kbytes sa10-sa8 00001xxx, 00010xxx, 00011xxx 192 (3x64) kbytes sa7 00000111 8 kbytes sa6 00000110 8 kbytes sa5 00000101 8 kbytes sa4 00000100 8 kbytes sa3 00000011 8 kbytes sa2 00000010 8 kbytes sa1 00000001 8 kbytes sa0 00000000 8 kbytes
18 am29sl160c november 1, 2004 the primary method requires v id on the reset# pin only, and is implemented either in-system or via pro- gramming equipment. figure 1, on page 19 shows the algorithms and figure 24, on page 45 shows the timing diagram. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method intended only for programming equipment requires v id on address pin a9 and oe#. this method is compatible with programmer routines written for earlier 3.0 volt-only amd flash devices. pub- lication number 21622 contains further details. contact an amd representative to request the document con- taining further details. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is protected or unprotected. see ?autoselect mode? on page 16 for details. write protect (wp#) the write protect function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the two ?outermost? 8 kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in ?sector/sector block protection and unprotection? on page 17 . the two out- ermost 8 kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-con- figured device, or the two sectors containing the highest addresses in a top-boot-configured device. if the system asserts v ih on the wp#/acc pin, the device reverts to whether the two outermost 8 kbyte boot sectors were last set to be protected or unpro- tected. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in ?sector/sector block protection and unprotection? on page 17 . note that if the system asserts v hh on the wp#/acc pin, all sectors, including the two outermost sectors, are unprotected. v hh is intended for accelerated in- system programming of the device during system pro- duction. it is advisable, therefore, not to assert v hh on this pin after the system has been placed in the field for use. if faster programming is desired, the system may use the unlock bypass program command sequence. temporary sector unprotect this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly pro- tected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously protected sectors are protected again. figure 2, on page 20 shows the algorithm, and figure 22, on page 44 shows the timing diagrams, for this feature.
november 1, 2004 am29sl160c 19 figure 1. in-system sector protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary secto r unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no s ector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
20 am29sl160c november 1, 2004 figure 2. temporar y sector unprotect operation secured silicon (secsi) sector flash memory region the secured silicon (secsi) sector is a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector in this device is 256 bytes in length. the device contains a secsi sector indicator bit that allows the system to determine whether or not the secsi sector was factory locked. this indicator bit is permanently set at the factory and cannot be changed, which prevents a factory-locked part from being cloned. amd offers this device only with the secsi sector factory serialized and locked. the first sixteen bytes of the secsi sector contain a random esn. to utilize the remainder secsi sector space, customers must provide their code to amd through amd?s express flash service. the factory will program and perma- nently protect the secsi sector (in addition to programming and protecting the remainder of the device as required). the system can read the secsi sector by writing the enter secsi sector command sequence (see ?enter secsi sector/exit secsi sector command sequence? on page 24 ). table 7, on page 20 shows the layout for the secsi sector. table 7. secsi sector addresses the device continues to read from the secsi sector until the system issues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 12, on page 28 for command definitions). in addition, the fol- lowing hardware data protection measures prevent accidental erasure or programming, which might other- wise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent uninten- tional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected. (if wp#/acc = v il , the outermost sectors remain protected) 2. all previously protected sectors are protected once again. description address range word mode (x16) byte mode (x8) 16-byte random esn 00?07h 000?00fh user-defined code or factory erased (all 1s) 08?7fh 010?0ffh
november 1, 2004 am29sl160c 21 common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-indepen- dent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in table 8, on page 21 to table 11, on page 23 . to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in table 8, on page 21 to table 11, on page 23 . the system must write the reset command to return the device to the autoselect mode. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/products/nvd/over- view/cfi.html. alternatively, contact an amd representative for copies of these documents. table 8. cfi query identification string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists)
22 am29sl160c november 1, 2004 table 9. system interface string table 10. device geometry definition addresses (word mode) addresses (byte mode) data description 1bh 36h 0018h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0022h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0004h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses (word mode) addresses (byte mode) data description 27h 4eh 0015h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 58h 0002h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 001eh 0000h 0000h 0001h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information
november 1, 2004 am29sl160c 23 table 11. primary vendor-specific extended query command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 12, on page 28 defines the valid reg- ister command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in ?ac characteristics? on page 37 . reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? on page 26 for more information on this mode. the system must issue the reset command to re- enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see ?reset com- mand? , next. see also ?requirements for reading array data? on page 11 for more information. the table provides the read parameters, and figure 13, on page 37 shows the timing diagram. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0030h minor version number, ascii 45h 8ah 0000h address sensitive unlock 0 = required, 1 = not required 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 01 = 29f040 mode, 02 = 29f016 mode, 03 = 29f400 mode, 04 = 29lv800a mode 4ah 94h 0000h simultaneous operation 00 = not supported, 01 = supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page
24 am29sl160c november 1, 2004 before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). see ?ac characteristics? on page 37 for parameters, and to figure 14, on page 38 for the timing diagram. autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table 12, on page 28 shows the address and data requirements. this method is an alternative to that shown in table 4, on page 16 , which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufacturer code. a read cycle at address 01h in word mode (or 02h in byte mode) returns the device code. a read cycle containing a sector address (sa) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. refer to table 2, on page 14 and table 3, on page 15 for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. enter secsi sector/exit secsi sector com- mand sequence the secsi sector region provides a secured data area containing a random, sixteen-byte electronic serial number (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi command sequence. the exit secsi command sequence returns the device to normal operation. table 12, on page 28 shows the address and data requirements for both command sequences. see also ?secured silicon (secsi) sector flash memory region? on page 20 for further information. word/byte program command sequence the system may program the device by word or byte, depending on the state of the byte# pin. program- ming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or tim- ings. the device automatically generates the program pulses and verifies the programmed cell margin. table 12, on page 28 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/by#. see ?write operation status? on page 29 for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program- ming operation. the byte program command sequence should be reinitiated once the device resets to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may halt the operation and set dq5 to ?1?, or cause the data# polling algorithm to indicate the operation was suc- cessful. however, a succeeding read shows that the data is still ?0?. only erase operations can convert a ?0? to a ?1?. unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two- cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. table 12, on page 28 shows the requirements for the command sequence.
november 1, 2004 am29sl160c 25 during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t cares. the device then returns to reading array data. the device offers accelerated program operations through the wp#/acc pin. this function is intended only to speed in-system programming of the device during system production. when the system asserts v hh on the wp#/acc pin, the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh for any operation other than accelerated programming, or device damage may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. figure 3 illustrates the algorithm for the program oper- ation. see ?erase/program operations? on page 40 for parameters, and figure 17, on page 41 for timing diagrams. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 12, on page 28 for program command sequence. figure 3. program operation
26 am29sl160c november 1, 2004 chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 12, on page 28 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. note that a hardware reset during the chip erase operation imme- diately terminates the operation. the chip erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. the system can determine the status of the erase oper- ation by using dq7, dq6, dq2, or ry/by#. see ?write operation status? on page 29 for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 4, on page 27 illustrates the algorithm for the erase operation. see ?erase/program operations? on page 40 for parameters, and figure 18, on page 42 for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. table 12, on page 28 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts are re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see ?dq3: sector erase timer? on page 31 .) the time-out begins from the rising edge of the final we# pulse in the command sequence. once the sector erase operation begins, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immediately terminates the operation. the sector erase command sequence should be rein- itiated once the device returns to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. (refer to ?write operation status? on page 29 for information on these status bits.) figure 4, on page 27 illustrates the algorithm for the erase operation. refer to the ?erase/program opera- tions? on page 40 for parameters, and to figure 18, on page 42 for timing diagrams. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algo- rithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately ter- minates the time-out period and suspends the erase operation.
november 1, 2004 am29sl160c 27 after the erase operation is suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see ?write operation status? on page 29 for information on these status bits. after an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? on page 29 for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see ?autoselect command sequence? on page 24 for more information. the system must write the erase resume command (address bits are ?don?t care?) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device resumes erasing. notes: 1. see table 12, on page 28 for erase command sequence. 2. see ?dq3: sector erase timer? on page 31 for more in- formation. figure 4. erase operation start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress
28 am29sl160c november 1, 2004 command definitions table 12. am29sl160c command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a19?a12 uniquely select any sector. notes: 1. see table 1, on page 11 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t cares in byte mode. 5. unless otherwise noted, address bits a19?a11 are don?t cares. 6. no unlock or command cycles required when in read mode. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when in the autoselect mode, or if dq5 goes high (while providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a protected sector. data bits dq15?dq8 are don?t care. see the autoselect command sequence section for more information. 10. the unlock bypass command is required prior to the unlock bypass program command. 11. the unlock bypass reset command is required to return to the read mode when in the unlock bypass mode. 12. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 13. the erase resume command is valid only during the erase suspend mode. 14. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 555 90 x00 01 byte aaa 555 aaa device id (top boot/bottom boot) word 4 555 aa 2aa 55 555 90 x01 22e4/ 22e7 byte aaa 555 aaa x02 e4/e7 secsi sector factory protect word 4 555 aa 2aa 55 555 90 x03 byte aaa 555 aaa x06 sector protect verify (note 9) word 4 555 aa 2aa 55 555 90 (sa)x02 byte aaa 555 aaa (sa)x04 enter secsi sector region word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa exit secsi sector region word 4 555 aa 2aa 55 555 90 xxx 00 byte aaa 555 aaa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 10) 2 xxx a0 pa pd unlock bypass reset (note 11) 2 ba 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 12) 1 ba b0 erase resume (note 13) 1 ba 30 cfi query (note 14) word 1 55 98 byte aa
november 1, 2004 am29sl160c 29 write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, dq7, and ry/by#. table 13, on page 32 and the following subsections describe the functions of these bits. dq7 and dq6 each offer a method for deter- mining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or is completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase sus- pend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then the device returns to reading array data. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to ?1?; prior to this, the device outputs the ?complement,? or ?0.? the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects dq7 changes from the com- plement to true data, it can read valid data at dq7? dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. figure 19, on page 43 , data# polling timings (during embedded algorithms), in the ?ac characteristics? section illus- trates this. table 13, on page 32 shows the outputs for data# polling on dq7. figure 5, on page 29 shows the data# polling algorithm. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 5. data# polling algorithm
30 am29sl160c november 1, 2004 ry/by#: ready/busy# ry/by# is a dedicated, open-drain output pin that indi- cates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 13, on page 32 shows the outputs for ry/by#. figure 14, on page 38 , figure 17, on page 41 and figure 18, on page 42 shows ry/by# for reset, pro- gram, and erase operations, respectively. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle (the system may use either oe# or ce# to control the read cycles). when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are pro- tected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on ?dq7: data# polling? on page 29 ). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 13, on page 32 shows the outputs for toggle bit i on dq6. figure 6, on page 31 shows the toggle bit algorithm. figure 20, on page 43 shows the toggle bit timing diagrams. figure 21, on page 44 shows the dif- ferences between dq2 and dq6 in graphical form. see also the subsection on ?dq2: toggle bit ii? . dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. the device toggles dq2 with each oe# or ce# read cycle. dq2 toggles when the system reads at addresses within those sectors that were selected for erasure. but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 13, on page 32 to compare outputs for dq2 and dq6. figure 6, on page 31 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the ?dq6: toggle bit i? subsection. figure 20, on page 43 shows the toggle bit timing diagram. figure 21, on page 44 shows the differ- ences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6, on page 31 for the following discus- sion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as dq5 went high. if the toggle bit is no longer toggling, the device successfully completed the program or erase operation. if it is still toggling, the
november 1, 2004 am29sl160c 31 device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 is not high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the begin- ning of the algorithm when it returns to determine the status of the operation (top of figure 6 ). dq5: exceeded timing limits dq5 indicates whether the program or erase time exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation exceeds the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation began. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out is complete, dq3 switches from ?0? to ?1.? if the time between additional sector erase commands from the system are assumed to be less than 50 s, the system need not monitor dq3. see also the ?sector erase command sequence? on page 26 . after the sector erase command sequence is written, the system should read the status on dq7 (data# polling) or dq6 (toggle bit i) to ensure the device accepted the command sequence, and then read dq3. if dq3 is ?1?, the internally controlled erase cycle started; all further commands (other than erase sus- pend) are ignored until the erase operation is complete. if dq3 is ?0?, the device accepts additional sector erase commands. to ensure the command is accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 13, on page 32 shows the outputs for dq3. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to ?1?. see text. figure 6. toggle bit algorithm (notes 1, 2) (note 1)
32 am29sl160c november 1, 2004 table 13. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation exceeds the maximum timing limits. see ?dq5: exceeded timing limits? on page 31 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
november 1, 2004 am29sl160c 33 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1). . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v a9 , oe# , and reset# (note 2) . . . . . . . . ?0.5 v to +11.0 v all other pins (note 1) . . . . . ?0.5 v to v cc + 0.5 v output short circuit current (note 3) . . . . . . 100 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 7 . maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 8 . 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is ?0.5 v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 7 . maximum dc input voltage on pin a9 is +11.0 v which may overshoot to +12.5 v for periods up to 20 ns. maximum dc input voltage on pin wp#/acc is +10.0 v which may overshoot to +11.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . . 0c to +70c industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c v cc supply voltages v cc , all speed options . . . . . . . . . . . .+1.8 v to +2.2 v operating ranges define those limits between which the func- tionality of the device is guaranteed. 20 ns 20 ns 0.0 v ?0.5 v 20 ns ?2.0 v figure 7. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 8. maximum positive overshoot waveform
34 am29sl160c november 1, 2004 dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than 1 ma/mhz, with oe# at v il . typical v cc is 2.0 v. 2. the maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 50 ns. 5. not 100% tested. parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 11.0 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1, 2) ce# = v il, oe# = v ih, byte mode 5 mhz 5 10 ma 1 mhz 1 3 ce# = v il, oe# = v ih, word mode 5 mhz 5 10 1 mhz 1 3 i cc2 v cc active write current (notes 2, 3, 5) ce# = v il, oe# = v ih 20 30 ma i cc3 v cc standby current (note 2) ce#, reset# = v cc 0.2 v 1 5 a i cc4 v cc reset current (note 2) reset# = v ss 0.2 v 1 5 a i cc5 automatic sleep mode (notes 2, 3) v ih = v cc 0.2 v; v il = v ss 0.2 v 15a v il input low voltage ?0.5 0.2 x v cc v v ih input high voltage 0.8 x v cc v cc + 0.3 v v hh voltage for wp#/acc sector protect/unprotect and program acceleration 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.0 v 9.0 11.0 v v ol output low voltage i ol = 100 a, v cc = v cc min 0.1 v oh output high voltage i oh = ?100 a, v cc = v cc min v cc ?0.1 v lko low v cc lock-out voltage (note 4) 1.2 1.5 v
november 1, 2004 am29sl160c 35 dc characteristics (continued) zero power flash 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns note: addresses are switching at 1 mhz figure 9. i cc1 current vs. time (showing acti ve and automatic sleep currents) 10 8 4 0 12345 frequency in mhz supply current in ma note: t = 25 c figure 10. typical i cc1 vs. frequency 1.8 v 2.2 v 2 6
36 am29sl160c november 1, 2004 test conditions table 14. test specifications key to switching waveforms c l device under te s t figure 11. test setup test condition -90, -100 -120, -150 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0?2.0 v input timing measurement reference levels 1.0 v output timing measurement reference levels 1.0 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 2.0 v 0.0 v 1.0 v 1.0 v output measurement level input figure 12. input waveforms and measurement levels
november 1, 2004 am29sl160c 37 ac characteristics read operations notes: 1. not 100% tested. 2. see figure 11, on page 36 and table 14, on page 36 for test specifications. . parameter description speed option jedec std test setup -90 -100 -120 -150 unit t avav t rc read cycle time (note 1) min 90 100 120 150 ns t avqv t acc address to output delay ce# = v il oe# = v il max 90 100 120 150 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 120 150 ns t glqv t oe output enable to output delay max 35 35 50 65 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 30 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 0 ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t oh figure 13. read operations timings
38 am29sl160c november 1, 2004 ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options jedec std test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read (see note) min 200 ns t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 14. reset# timings
november 1, 2004 am29sl160c 39 ac characteristics word/byte configuration (byte#) parameter description speed options jedec std -90 -100 -120 -150 unit t elfl/ t elfh ce# to byte# switching low or high max 10 ns t flqz byte# switching low to output high z max 50 50 60 60 ns t fhqv byte# switching high to output active min 90 100 120 150 ns dq15 output data output (dq0?dq7) ce# oe# byte# t elfl dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t flqz byte# switching from word to byte mode dq15 output data output (dq0?dq7) byte# t elfh dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t fhqv byte# switching from byte to word mode figure 15. byte# timings for read operations note: refer to the erase/program operations table for t as and t ah specifications. figure 16. byte# timings for write operations ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
40 am29sl160c november 1, 2004 ac characteristics erase/program operations notes: 1. not 100% tested. 2. see ?erase and programming performance? on page 48 for more information. parameter speed options jedec std description -90 -100 -120 -150 unit t avav t wc write cycle time (note 1) min 90 100 120 150 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min50506070ns t dvwh t ds data setup time min50506070ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 50 50 60 70 ns t whwl t wph write pulse width high min 30 ns t whwh1 t whwh1 programming operation (notes 1, 2) byte typ 10 s word typ 12 accelerated program operation, byte or word (note 2) typ 8 s t whwh2 t whwh2 sector erase operation (notes 1, 2) typ 2 sec t vcs v cc setup time min 50 s t rb recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay min 200 ns
november 1, 2004 am29sl160c 41 ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. figure 17. program operation timings
42 am29sl160c november 1, 2004 ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?). 2. illustration shows device in word mode. figure 18. chip/sector erase operation timings
november 1, 2004 am29sl160c 43 ac characteristics we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true a ddresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read c ycle. figure 19. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 ry/by# t busy addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 20. toggle bit timings (during embedded algorithms)
44 am29sl160c november 1, 2004 ac characteristics temporary sector unprotect parameter all speed options jedec std description unit t vidr v id rise and fall time min 500 ns t vhh v hh rise and fall time min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s note: the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an erase-suspended sector. figure 21. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing r eset# t vidr v id 0 or 1.8 v ce# we# ry/by# t vidr t rsp program or erase command sequence 0 or 1.8 v figure 22. temporary sector unprotect timing diagram
november 1, 2004 am29sl160c 45 ac characteristics figure 23. accelerated program timing diagram w p#/acc t v hh v hh v il or v i h t v hh v il or v ih sector protect: 150 s sector unprot ect: 15 ms 1 s r eset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. figure 24. sector protect/ unprotect timing diagram
46 am29sl160c november 1, 2004 ac characteristics alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. see ?erase and programming performance? on page 48 for more information. parameter speed options jedec std description -90 -100 -120 -150 unit t avav t wc write cycle time (note 1) min 90 100 120 150 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 50 50 60 70 ns t dveh t ds data setup time min 50 50 60 70 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 50 50 60 70 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 programming operation (notes 1, 2) byte typ 10 s word typ 12 accelerated program operation, byte or word (note 2) typ 8 s t whwh2 t whwh2 sector erase operation (notes 1, 2) typ 2 sec
november 1, 2004 am29sl160c 47 ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. pa = program address, pd = program data, dq7# = complement of the data written, d out = data written 2. figure indicates the last two bus cycles of command sequence. 3. word mode address used as an example. figure 25. alternate ce# contro lled write operation timings
48 am29sl160c november 1, 2004 erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 2.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 1.8 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 12, on page 28 for further information on command definitions. 6. the device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles. latchup characteristics includes all pins except v cc . test conditions: v cc = 1.8 v, one pin at a time. tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 2 15 s excludes 00h programming prior to erasure (note 4) chip erase time 70 s byte programming time 10 300 s excludes system level overhead (note 5) word programming time 12 360 s accelerated program time, word/byte 8 240 s chip programming time (note 3) byte mode 20 160 s word mode 14 120 s description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 11.0 v input voltage with respect to v ss on all i/o pins ?0.5 v v cc + 0.5 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf parameter test conditions min unit minimum pattern data retention time 150 c10 years 125 c20 years
november 1, 2004 am29sl160c 49 physical dimensions* ts 048?48-pin standard tsop * for reference only. bsc is an ansi standard for basic space centering. dwg rev aa; 10/99
50 am29sl160c november 1, 2004 physical dimensions fbc048?48-ball fine-pitch ball grid array (fbga) 8 x 9 mm package dwg rev af; 10/99
november 1, 2004 am29sl160c 51 revision summary revision a (december 1998) initial release. revision a+1 (january 1999) distinctive characteristics wp#/acc pin: in the third subbullet, deleted reference to increased erase performance. device bus operations accelerated program and erase operations: deleted all references to accelerated erase. sector/sector block protection and unprotection: changed section name and text to include tables and references to sector block protection and unprotection. ac characteristics accelerated program timing diagram: deleted refer- ence in title to accelerated erase. revision a+2 (march 23, 1999) connection diagrams corrected the tsop pinout on pins 13 and 14. revision a+3 (april 12, 1999) global modified the description of accelerated programming to emphasize that it is intended only to speed in-system programming of the device during the system produc- tion process. distinctive characteristics secured silicon (secsi) sector bullet: added the 8- byte unique serial number to description. device bus operations table modified note 3 to indicate sector protection behavior when v ih is asserted on wp#/acc. applied note 3 to the wp#/acc column for write operations. ordering information added the ?n? designator to the optional processing section. secured silicon (secsi) sector flash memory region modified explanatory text to indicate that devices now have an 8-byte unique esn in addition to the 16-byte random esn. added table for address range clarification. revision a+4 (may 14, 1999) global deleted all references to the unique esn. revision a+5 (july 23, 1999) global added 90 ns speed option. revision a+6 (september 1, 1999) ac characteristics hardware reset (reset#) table: deleted t rpd specifi- cation. erase/program operations table: deleted t oes specification. revision a+7 (september 7, 1999) distinctive characteristics ultra low power consumption bullet: corrected values to match those in the dc characteristics table. ac characteristics alternate ce# controlled erase/program operations: deleted t oes specification. revision b (december 14, 1999) ac characteristics? figure 17 . program operations timing and figure 18 . chip/sector erase operations deleted t ghwl and changed oe# waveform to start at high. physical dimensions replaced figures with more detailed illustrations. revision c (february 21, 2000) removed ?advance information? designation from data sheet. data sheet parameters are now stable; only speed, package, and temperature range combinations are expected to change in future revisions. device bus operations table changed standby voltage specification to v cc 0.2 v. standby mode changed standby voltage specification to v cc 0.2 v. dc characteristics table changed test conditions for i cc3 , i cc4 , i cc5 to v cc 0.2 v. revision c+1 (november 14, 2000) global added dash to speed options and opns. added table of contents. ac characteristics?read operations changed t df to 16 ns for all speeds.
52 am29sl160c november 1, 2004 revision c+2 (june 11, 2002) secured silicon (secsi) sector flash memory region deleted reference to a-1 not being used in addressing, and to address bits that are don?t cares. in ta b l e 7 , changed lower address bit for user-defined code to 08h (word mode) and 010h (byte mode). revision c+3 (november 1, 2004) global added colophon. added reference links. ordering information added temperature ranges for pb-free package valid combinations for tsop packages added ed, and ef combinations. valid combinations for fbga packages added wcd, and wcf to order number column, and added d, and f to package marking column. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general offi ce use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion llc will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operat- ing conditions. if any products described in this document represent goods or technologies subject to certain restrictions on e xport under the foreign exchange and foreign trade law of japan , the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks copyright ? 2000 -2004 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regi stered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies

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